The present invention relates to a sense amplifier for use in a content addressable memory (CAM) array.
A compare operation within a CAM array is typically performed by charging a large number of match lines to a VDD supply voltage. If a match condition exists on a particular match line, the match line will remain charged at the VDD supply voltage. If no match condition exists on a particular match line, then this match line is pulled down to the VSS supply voltage (i.e., ground). Typically, many non-match conditions will exist for each compare operation. Thus, each compare operation consists of charging and discharging many match lines across the full VDD supply voltage. As a result, a conventional CAM array consumes a large amount of power. In general, the match lines are subjected to a relatively large signal swing in order to allow the state of the match signal to be accurately sensed.
It would therefore be desirable to have an improved sense amplifier that is able to sense smaller match line signal swings.
Accordingly, the present invention provides a sense amplifier that operates in response to a voltage swing as small as the difference between two transistor threshold voltages.
In accordance with one embodiment, a sense amplifier includes a first transistor that is used to pre-charge a match line of a CAM array. The first transistor is coupled between the VDD supply terminal and the match line. During the pre-charge operation, the gate of the first transistor is coupled to receive a reference voltage VREF. As a result, the match line is pre-charged to a voltage equal to VREF minus VT1, where VT1 is the threshold voltage of the first transistor. The reference voltage VREF is selected to be less than the VDD supply voltage in order to achieve power savings.
The sense amplifier also includes a storage node that is pre-charged to the VDD supply voltage. The state of the storage node is used to determine whether a match or non-match condition exists on the match line during a compare operation.
A second transistor is coupled between the match line and the storage node of the sense amplifier. The gate of the second transistor is coupled to a dummy line of the CAM array. The dummy line is pre-charged to a voltage equal to the reference voltage VREF. As a result, the gate-to-source voltage VGS of the second transistor is equal to VT1 (i.e., or the difference between the gate voltage (VREF) and the match line voltage (VREFxe2x88x92VT1)). The second transistor is designed to have a second threshold voltage VT2, which is greater than the threshold voltage of the first transistor, VT1. As a result, the second transistor is initially turned off.
During a compare operation, a row of CAM cells coupled to the match line will exhibit a match condition or a non-match condition. If a match condition exists, the match line remains at a voltage of VREFxe2x88x92VT1. The second transistor remains off under these conditions, thereby allowing the storage node to remain at a logic high state.
If a non-match condition exists, the match line is pulled down toward ground. As soon as the match line is pulled down to a voltage equal to VREF minus VT2, the second transistor is turned on, thereby pulling down the storage node to a logic low state. Note that the voltage swing required by the sense amplifier is equal to the difference between the first and second threshold voltages (i.e., VT2xe2x88x92VT1).
In one variation, the sense amplifier is expanded such that a second match line is coupled to the storage node in the same manner as the first match line. In this case, the two match lines correspond with a single row of the CAM array.
In accordance with another aspect of the present invention, a current mirror circuit is coupled to the storage node, thereby supplying a small constant current to the storage node. This constant current helps to maintain the logic high state of the storage node during non-match conditions.
The present invention will be more fully understood in view of the following description and drawings.